In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
All practical software hardening schemes, as well as practical encryption schemes, e.g., AES, were not proven to be secure. One technique to enhance security is robust combiners. A...
Recently, there has been significant interest in developing space and time efficient solutions for answering continuous summarization queries over data streams. While these techni...
Nagender Bandi, Ahmed Metwally, Divyakant Agrawal,...
The motivation and objective for this paper is to demonstrate “Personal High Performance Computing (PHPC)”, which requires only a smaller number of computers, resources and sp...