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CGO
2004
IEEE
15 years 11 months ago
Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors
Pre-execution techniques have received much attention as an effective way of prefetching cache blocks to tolerate the everincreasing memory latency. A number of pre-execution tech...
Dongkeun Kim, Shih-Wei Liao, Perry H. Wang, Juan d...
CODES
2004
IEEE
15 years 11 months ago
Operation tables for scheduling in the presence of incomplete bypassing
Register bypassing is a powerful and widely used feature in modern processors to eliminate certain data hazards. Although complete bypassing is ideal for performance, bypassing ha...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CSMR
2004
IEEE
15 years 11 months ago
Supporting Architectural Restructuring by Analyzing Feature Models
In order to lower the risk, reengineering projects aim at high reuse rates. Therefore, tasks like architectural restructuring have to be performed in a way that developed new syst...
Ilian Pashov, Matthias Riebisch, Ilka Philippow
EWSA
2006
Springer
15 years 10 months ago
On the Modular Representation of Architectural Aspects
An architectural aspect is a concern that cuts across architecture ty units and cannot be effectively modularized using the given abstractions of conventional Architecture Descript...
Alessandro Garcia, Christina Chavez, Thaís ...
FASE
2006
Springer
15 years 10 months ago
Regular Inference for State Machines with Parameters
Techniques for inferring a regular language, in the form of a finite automaton, from a sufficiently large sample of accepted and nonaccepted input words, have been employed to cons...
Therese Berg, Bengt Jonsson, Harald Raffelt
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