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ISLPED
2004
ACM
137views Hardware» more  ISLPED 2004»
15 years 12 months ago
Location cache: a low-power L2 cache system
While set-associative caches incur fewer misses than directmapped caches, they typically have slower hit times and higher power consumption, when multiple tag and data banks are p...
Rui Min, Wen-Ben Jone, Yiming Hu
SIGCOMM
2010
ACM
15 years 6 months ago
How internet concepts and technologies can help green and smarten the electrical grid
Several powerful forces are gathering to make fundamental and irrevocable changes to the century-old grid. The nextgeneration grid, often called the `smart grid,' will featur...
Srinivasan Keshav, Catherine Rosenberg
ICCD
2004
IEEE
107views Hardware» more  ICCD 2004»
16 years 3 months ago
Network-on-Chip: The Intelligence is in The Wire
In this paper we describe how Network-on-Chip (NoC) will be the next major challenge to implementing complex and function-rich applications in advanced manufacturing processes at ...
Gérard Mas, Philippe Martin
GECCO
2007
Springer
300views Optimization» more  GECCO 2007»
16 years 20 days ago
A NSGA-II, web-enabled, parallel optimization framework for NLP and MINLP
Engineering design increasingly uses computer simulation models coupled with optimization algorithms to find the best design that meets the customer constraints within a time con...
David J. Powell, Joel K. Hollingsworth
DAC
2007
ACM
16 years 7 months ago
Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors
Minimizing power consumption is vitally important in embedded system design; power consumption determines battery lifespan. Ultralow-power designs may even permit embedded systems...
Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert ...