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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 12 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
TC
2008
15 years 6 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
VLSISP
2008
129views more  VLSISP 2008»
15 years 6 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
15 years 8 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston
USITS
2001
15 years 8 months ago
An Architecture for Content Routing Support in the Internet
The primary use of the Internet is content distribution -- the delivery of web pages, audio, and video to client applications -- yet the Internet was never architected for scalabl...
Mark Gritter, David R. Cheriton