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LCTRTS
2004
Springer
15 years 11 months ago
Dynamic voltage scaling for real-time multi-task scheduling using buffers
This paper proposes energy efficient real-time multi-task scheduling (EDF and RM) algorithms by using buffers. The buffering technique overcomes a drawback of previous approaches ...
Chaeseok Im, Soonhoi Ha
ICMCS
2005
IEEE
158views Multimedia» more  ICMCS 2005»
15 years 12 months ago
Processor Load Analysis for Mobile Multimedia Streaming: The Implication of Power Reduction
The software codec on mobile device introduces significant power consumption because the energy efficiency of general processor based system is much lower than that of the dedicat...
Min Li, Xiaobo Wu, Zihua Guo, Richard Yao, Xiaolan...
LCPC
2005
Springer
15 years 11 months ago
Compiler Control Power Saving Scheme for Multi Core Processors
With the increase of transistors integrated onto a chip, multi core processor architectures have attracted much attention to achieve high effective performance, shorten developmen...
Jun Shirako, Naoto Oshiyama, Yasutaka Wada, Hiroak...
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 11 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
DAC
2003
ACM
16 years 7 months ago
Scalable modeling and optimization of mode transitions based on decoupled power management architecture
To save energy, many power management policies rely on issuing mode-change commands to the components of the system. Efforts to date have focused on how these policies interact wi...
Dexin Li, Qiang Xie, Pai H. Chou