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ISCA
2010
IEEE
170views Hardware» more  ISCA 2010»
15 years 11 months ago
Relax: an architectural framework for software recovery of hardware faults
As technology scales ever further, device unreliability is creating excessive complexity for hardware to maintain the illusion of perfect operation. In this paper, we consider whe...
Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaral...
CODES
2004
IEEE
15 years 10 months ago
Optimizing the memory bandwidth with loop fusion
The memory bandwidth largely determines the performance and energy cost of embedded systems. At the compiler level, several techniques improve the memory bandwidth at the scope of...
Paul Marchal, José Ignacio Gómez, Fr...
JCC
2011
133views more  JCC 2011»
15 years 1 months ago
MIBPB: A software package for electrostatic analysis
: The Poisson–Boltzmann equation (PBE) is an established model for the electrostatic analysis of biomolecules. The development of advanced computational techniques for the soluti...
Duan Chen, Zhan Chen, Changjun Chen, Weihua Geng, ...
ISPDC
2010
IEEE
15 years 4 months ago
Resource-Aware Compiler Prefetching for Many-Cores
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
George C. Caragea, Alexandros Tzannes, Fuat Keceli...
ICCAD
2010
IEEE
186views Hardware» more  ICCAD 2010»
15 years 4 months ago
Application-Aware diagnosis of runtime hardware faults
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Currently available online t...
Andrea Pellegrini, Valeria Bertacco