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CGO
2004
IEEE
15 years 10 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
ASWSD
2006
Springer
15 years 10 months ago
Generating Sound and Resource-Aware Code from Hybrid Systems Models
Modern real-time embedded systems are complex, distributed, feature-rich applications. Model-based development of real-time embedded systems promises to simplify and accelerate the...
Madhukar Anand, Sebastian Fischmeister, Jesung Kim...
TSE
2008
89views more  TSE 2008»
15 years 6 months ago
WASP: Protecting Web Applications Using Positive Tainting and Syntax-Aware Evaluation
Many software systems have evolved to include a Web-based component that makes them available to the public via the Internet and can expose them to a variety of Web-based attacks. ...
William G. J. Halfond, Alessandro Orso, Pete Manol...
CAL
2008
15 years 5 months ago
Transaction-Aware Network-on-Chip Resource Reservation
Packet-switched interconnect fabric, widely viewed as the de facto on-chip data communication standard in the many-core era, offers high throughput and excellent scalability. Howev...
Zheng Li, Changyun Zhu, Li Shang, Robert P. Dick, ...
CAL
2010
15 years 3 months ago
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors
This paper describes dynamic pressure-aware associative placement (DPAP), a novel distributed cache management scheme for large-scale chip multiprocessors. Our work is motivated by...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem