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ISCAS
2003
IEEE
107views Hardware» more  ISCAS 2003»
16 years 5 days ago
On chip Gaussian processing for high resolution CMOS image sensors
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...
Sri Vinayagamoorthy, Richard Hornsey
AHS
2007
IEEE
211views Hardware» more  AHS 2007»
15 years 11 months ago
Synthesis of Multimode digital signal processing systems
In this paper, we propose a design methodology for implementing a multimode (or multi-configuration) and multi-throughput system into a single hardware architecture. The inputs of...
Caaliph Andriamisaina, Emmanuel Casseau, Philippe ...
DAC
2010
ACM
15 years 10 months ago
Performance yield-driven task allocation and scheduling for MPSoCs under process variation
With the ever-increasing transistor variability in CMOS technology, it is essential to integrate variation-aware performance analysis into the task allocation and scheduling proce...
Lin Huang, Qiang Xu
CBSE
2006
Springer
15 years 10 months ago
A Process for Resolving Performance Trade-Offs in Component-Based Architectures
Designing architectures requires the balancing of multiple system quality objectives. In this paper, we present techniques that support the exploration of the quality properties of...
Egor Bondarev, Michel R. V. Chaudron, Peter H. N. ...
FPL
2006
Springer
137views Hardware» more  FPL 2006»
15 years 10 months ago
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations
Both custom IC and FPGA designs in the nanometer regime suffer from process variations. But different from custom ICs, FPGAs' programmability offers a unique design freedom t...
Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton