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ISLPED
2006
ACM
119views Hardware» more  ISLPED 2006»
16 years 23 days ago
Process variation aware cache leakage management
In a few technology generations, limitations of fabrication processes will make accurate design time power estimates a daunting challenge. Static leakage current which comprises a...
Ke Meng, Russ Joseph
FPL
2008
Springer
175views Hardware» more  FPL 2008»
15 years 8 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen
EOR
2006
178views more  EOR 2006»
15 years 6 months ago
A fuzzy optimization model for QFD planning process using analytic network approach
In both the quality improvement and the design of a product, the engineering characteristics affecting product performance are primarily identified and improved to optimize custom...
Cengiz Kahraman, Tijen Ertay, Gülçin B...
DAC
2011
ACM
14 years 6 months ago
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhr...
DAC
2008
ACM
16 years 7 months ago
An area-efficient high-throughput hybrid interconnection network for single-chip parallel processing
Single-chip parallel processing requires high bandwidth between processors and on-chip memory modules. A recently proposed Mesh-of-Trees (MoT) network provides high throughput and...
Aydin O. Balkan, Gang Qu, Uzi Vishkin