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VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
16 years 7 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
16 years 1 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
MOBICOM
2006
ACM
16 years 21 days ago
The design, deployment, and analysis of signetLab: a sensor network testbed and interactive management tool
Abstract-The emergence of small, inexpensive, networkcapable sensing devices led to a great deal of research on the design and implementation of sensor networks. A critical step in...
Riccardo Crepaldi, Simone Friso, Albert F. Harris ...
DAC
1997
ACM
15 years 11 months ago
A C-Based RTL Design Verification Methodology for Complex Microprocessor
Cr, As the complexity of high-performance microprocessor increases, functional verification becomes more and more difficult and RTL simulation emerges as the bottleneck of the des...
Joon-Seo Yim, Yoon-Ho Hwang, Chang-Jae Park, Hoon ...
206
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PATMOS
2000
Springer
15 years 10 months ago
Early Power Estimation for System-on-Chip Designs
Abstract. Reduction of chip packaging and cooling costs for deep sub-micron SystemOn-Chip (SOC) designs is an emerging issue. We present a simulation-based methodology able to real...
Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reo...