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189
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IESS
2007
Springer
16 years 27 days ago
2007
Springer
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
218
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ECRTS
2006
IEEE
16 years 25 days ago
2006
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
184
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ISCA
2003
IEEE
16 years 1 days ago
2003
IEEE
Meeting deadlines is a key requirement in safe realtime systems. Worst-case execution times (WCET) of tasks are needed for safe planning. Contemporary worst-case timing analysis t...
203
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AI
1998
Springer
15 years 6 months ago
1998
Springer
Renewed motives for space exploration have inspired NASA to work toward the goal of establishing a virtual presence in space, through heterogeneous eets of robotic explorers. Info...
232
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VLSID
2009
IEEE
16 years 7 months ago
2009
IEEE
Many system-level design tasks (e.g. timing analysis, hardware/software partitioning and design space exploration) involve computational kernels that are intractable (usually NP-ha...