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ARVLSI
1997
IEEE
151views VLSI» more  ARVLSI 1997»
15 years 10 months ago
The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors
A microprocessor integrated with DRAM on the same die has the potential to improve system performance by reducing the memory latency and improving the memory bandwidth. However, a...
Tadaaki Yamauchi, Lance Hammond, Kunle Olukotun
JVCA
2007
78views more  JVCA 2007»
15 years 7 months ago
Stable advection-reaction-diffusion with arbitrary anisotropy
Turing first theorized that many biological patterns arise through the processes of reaction and diffusion [1]. Subsequently, reaction-diffusion systems have been studied in ma...
Theodore Kim, Ming C. Lin
VLSISP
2008
123views more  VLSISP 2008»
15 years 7 months ago
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
ROBOCOMM
2007
IEEE
16 years 1 months ago
A networked robot system for wireless network emulation
Abstract—A major barrier to advancing modern wireless networking research is the lack of an effective wireless network simulation platform that simultaneously offers high fideli...
Tzi-cker Chiueh, Rupa Krishnan, Pradipta De, Jui-H...
IPSN
2005
Springer
16 years 23 days ago
eBlocks - an enabling technology for basic sensor based systems
—We describe the development of a set of embedded system building blocks, known as eBlocks. An eBlock network can be viewed as a basic form of sensor network that can be develope...
Susan Cotterell, Ryan Mannion, Frank Vahid, Harry ...