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RTAS
2008
IEEE
16 years 1 months ago
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
Multi-core chips have been increasingly adopted by microprocessor industry. For real-time systems to safely harness the potential of multi-core computing, designers must be able t...
Jun Yan, Wei Zhang
RTAS
2008
IEEE
16 years 1 months ago
Throttling On-Disk Schedulers to Meet Soft-Real-Time Requirements
To achieve better throughput, many hard drive manufacturers use internal queues and scheduling to take advantage of vendor-specific characteristics and knowledge. While this tren...
Mark J. Stanovich, Theodore P. Baker, An-I Andy Wa...
RTAS
2008
IEEE
16 years 1 months ago
A Modular Worst-case Execution Time Analysis Tool for Java Processors
Recent technologies such as the Real-Time Specification for Java promise to bring Java’s advantages to real-time systems. While these technologies have made Java more predictab...
Trevor Harmon, Martin Schoeberl, Raimund Kirner, R...
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
16 years 1 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...
CODES
2007
IEEE
16 years 1 months ago
Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
Iyad Al Khatib, Davide Bertozzi, Axel Jantsch, Luc...
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