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FPGA
2004
ACM
147views FPGA» more  FPGA 2004»
15 years 11 months ago
The SFRA: a corner-turn FPGA architecture
FPGAs normally operate at whatever clock rate is appropriate for the loaded configuration. When FPGAs are used as computational devices in a larger system, however, it is better ...
Nicholas Weaver, John R. Hauser, John Wawrzynek
ISCA
1999
IEEE
94views Hardware» more  ISCA 1999»
15 years 10 months ago
A Performance Comparison of Contemporary DRAM Architectures
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-bas...
Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor ...
ASAP
2004
IEEE
126views Hardware» more  ASAP 2004»
15 years 10 months ago
Hyper-Programmable Architectures for Adaptable Networked Systems
We explain how modern programmable logic devices have capabilities that are well suited for them to assume a central role in the implementation of networked systems, now and in th...
Gordon J. Brebner, Philip James-Roxby, Eric Keller...
DAC
1999
ACM
16 years 7 months ago
An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect
In this paper we present a new algorithm for computing reduced-order models of interconnect which utilizes the dominant controllable subspace of the system. The dominant controlla...
Jing-Rebecca Li, Frank Wang, Jacob White
DAC
2009
ACM
15 years 10 months ago
Reduction techniques for synchronous dataflow graphs
The Synchronous Dataflow (SDF) model of computation is popular for modelling the timing behaviour of real-time embedded hardware and software systems and applications. It is an es...
Marc Geilen