1379 search results - page 8 / 276 » Elements of low power design for integrated systems |
174
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DCC
2000
IEEE
15 years 10 months ago
2000
IEEE
We present a novel algorithm that assigns codes to instructions during instruction code compression in order to minimize bus-related bit-toggling and thus reducing power consumpti...
182
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ICCAD
2002
IEEE
16 years 2 months ago
2002
IEEE
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
150
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ISLPED
2005
ACM
15 years 11 months ago
2005
ACM
This paper proposes a non-uniform cache architecture for reducing the power consumption of memory systems. The nonuniform cache allows having different associativity values (i.e.,...
162
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TVLSI
2010
15 years 22 days ago
2010
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
151
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
— In this paper, we examine the impact of application task mapping on the reliability of MPSoC in the presence of single-event upsets (SEUs). We propose a novel soft erroraware d...