1379 search results - page 75 / 276 » Elements of low power design for integrated systems |
156
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NOCS
2010
IEEE
15 years 4 months ago
2010
IEEE
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
189
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IPSN
2005
Springer
15 years 11 months ago
2005
Springer
Abstract— Sustainable operation of battery powered wireless embedded systems (such as sensor nodes) is a key challenge, and considerable research effort has been devoted to energ...
149
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KES
2005
Springer
15 years 11 months ago
2005
Springer
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
131
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
167
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ISLPED
2003
ACM
15 years 11 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...