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» Elements of low power design for integrated systems
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DAC
2008
ACM
16 years 7 months ago
Scan chain clustering for test power reduction
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...
Christian G. Zoellin, Hans-Joachim Wunderlich, Jen...
DAC
2004
ACM
16 years 7 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
ICALT
2006
IEEE
16 years 7 days ago
The Design of Internet Collaborative Learning System with Embedded Load-Balancing Broker
To transplant the six characteristics of traditional collaborative learning into the network collaborative learning environment, this paper proposes the design of an Internet coll...
Fu-Chien Kao, Chia-Wei Liu, Zhi-Hua Ji, Chia-Liang...
EUROPAR
2005
Springer
15 years 11 months ago
Early Experience with Scientific Applications on the Blue Gene/L Supercomputer
Abstract. Blue Gene/L uses a large number of low power processors, together with multiple integrated interconnection networks, to build a supercomputer with low cost, space and pow...
George S. Almasi, Gyan Bhanot, Dong Chen, Maria El...
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
15 years 11 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell