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» Elements of low power design for integrated systems
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SEKE
2001
Springer
15 years 11 months ago
Temporal Logic Properties of Java Objects
ct 7 Applying finite-state verification techniques to software systems looks attractive because they are capable of detecting very subtle 8 defects in the logic design of these s...
Radu Iosif, Riccardo Sisto
IPPS
2000
IEEE
15 years 10 months ago
Three Dimensional VLSI-Scale Interconnects
As processor speeds rapidly approach the Giga-Hertz regime, the disparity between process time and memory access time plays an increasing role in the overall limitation of processo...
Dennis W. Prather
GLVLSI
2003
IEEE
310views VLSI» more  GLVLSI 2003»
15 years 11 months ago
54x54-bit radix-4 multiplier based on modified booth algorithm
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
GLVLSI
2008
IEEE
204views VLSI» more  GLVLSI 2008»
16 years 27 days ago
NBTI resilient circuits using adaptive body biasing
Reliability has become a practical concern in today’s VLSI design with advanced technologies. In-situ sensors have been proposed for reliability monitoring to provide advance wa...
Zhenyu Qi, Mircea R. Stan
MICRO
2002
IEEE
173views Hardware» more  MICRO 2002»
15 years 11 months ago
Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
Christoforos E. Kozyrakis, David A. Patterson