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» Elements of low power design for integrated systems
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ISCA
2008
IEEE
188views Hardware» more  ISCA 2008»
16 years 25 days ago
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron tech...
Dongkook Park, Soumya Eachempati, Reetuparna Das, ...
IADIS
2004
15 years 7 months ago
A distributed monitoring system with global network and Web technology
A distributed monitoring system has been developed, which is organized with network cameras, an integrated web/mail server, web-based clients including high-performance cellular p...
Yoshiro Imai, Daisuke Yamane, Osamu Sadayuki
ASPLOS
2010
ACM
15 years 9 months ago
Orthrus: efficient software integrity protection on multi-cores
This paper proposes an efficient hardware/software system that significantly enhances software security through diversified replication on multi-cores. Recent studies show that a ...
Ruirui Huang, Daniel Y. Deng, G. Edward Suh
ISCAS
2006
IEEE
135views Hardware» more  ISCAS 2006»
16 years 13 days ago
A sensor system on chip for wireless microsystems
Recent years have seen the rapid development of microsensor technology, system on chip design, wireless technology and ubiquitous computing. When assembled into a complex microsys...
L. Wang, Nizamettin Aydin, A. Astaras, M. Ahmadian...
CONEXT
2009
ACM
15 years 7 months ago
ARES: an anti-jamming reinforcement system for 802.11 networks
Dense, unmanaged 802.11 deployments tempt saboteurs into launching jamming attacks by injecting malicious interference. Nowadays, jammers can be portable devices that transmit int...
Konstantinos Pelechrinis, Ioannis Broustis, Srikan...