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» Elements of low power design for integrated systems
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ISORC
1999
IEEE
15 years 10 months ago
An Object-level Gateway Supporting Integrated-Property Quality of Service
As networks and the use of communication within applications continue to grow and find more uses, so too does the demand for more control and manageability of various "system...
Richard E. Schantz, John A. Zinky, David A. Karr, ...
FPGA
2007
ACM
153views FPGA» more  FPGA 2007»
16 years 17 days ago
GlitchLess: an active glitch minimization technique for FPGAs
This paper describes a technique that reduces dynamic power in FPGAs by reducing the number of glitches in the global routing resources. The technique involves adding programmable...
Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wil...
ISQED
2006
IEEE
94views Hardware» more  ISQED 2006»
16 years 13 days ago
System-Level SRAM Yield Enhancement
It is well known that SRAM constitutes a large portion of modern integrated circuits, with 80% or more of the total transistors being dedicated to SRAM in a typical processor or S...
Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park...
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
16 years 27 days ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
CDC
2008
IEEE
125views Control Systems» more  CDC 2008»
15 years 6 months ago
Efficient waypoint tracking hybrid controllers for double integrators using classical time optimal control
This paper is a response to requests from several respected colleagues in academia for a careful writeup of the classical time-optimal control based hybrid controllers that we have...
Haitham A. Hindi, Lara S. Crawford, Rong Zhou, Cra...