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FCCM
2009
IEEE
192views VLSI» more  FCCM 2009»
16 years 25 days ago
FPGA Floating Point Datapath Compiler
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
Martin Langhammer, Tom VanCourt
148
Voted
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
16 years 4 days ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
ISCAS
2005
IEEE
123views Hardware» more  ISCAS 2005»
15 years 11 months ago
Lower-bound estimation for multi-bitwidth scheduling
In high-level synthesis, accurate lower-bound estimation is helpful to explore the search space efficiently and to evaluate the quality of heuristic algorithms. For the lower-bound...
Junjuan Xu, Jason Cong, Xu Cheng
CONCUR
2005
Springer
15 years 11 months ago
A Compositional Approach to the Stochastic Dynamics of Gene Networks
We propose a compositional approach to the dynamics of gene regulatory networks based on the stochastic π-calculus, and develop a representation of gene network elements which can...
Luca Cardelli
GECCO
2005
Springer
127views Optimization» more  GECCO 2005»
15 years 11 months ago
Investigating the performance of module acquisition in cartesian genetic programming
Embedded Cartesian Genetic Programming (ECGP) is a form of the graph based Cartesian Genetic Programming (CGP) in which modules are automatically acquired and evolved. In this pap...
James Alfred Walker, Julian Francis Miller