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ITC
1998
IEEE
71views Hardware» more  ITC 1998»
15 years 11 months ago
A structured and scalable mechanism for test access to embedded reusable cores
The main objective of core-based IC design is improvement of design efficiency and time-to-market. In order to prevent test development from becoming the bottleneck in the entire ...
Erik Jan Marinissen, Robert G. J. Arendsen, Gerard...
MICRO
1998
IEEE
91views Hardware» more  MICRO 1998»
15 years 11 months ago
Effective Cluster Assignment for Modulo Scheduling
Clustering is one solution to the demand for wideissue machines and fast clock cycles because it allows for smaller, less ported register files and simpler bypass logic while rema...
Erik Nystrom, Alexandre E. Eichenberger
MICRO
1998
IEEE
129views Hardware» more  MICRO 1998»
15 years 11 months ago
A Bandwidth-efficient Architecture for Media Processing
Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are p...
Scott Rixner, William J. Dally, Ujval J. Kapasi, B...
ISPD
1998
ACM
99views Hardware» more  ISPD 1998»
15 years 11 months ago
CHDStd - application support for reusable hierarchical interconnect timing views
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
15 years 11 months ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar