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ISSS
2002
IEEE
139views Hardware» more  ISSS 2002»
15 years 11 months ago
Multiprocessor Mapping of Process Networks: A JPEG Decoding Case Study
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
Erwin A. de Kock
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
15 years 11 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 11 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISCA
2000
IEEE
121views Hardware» more  ISCA 2000»
15 years 11 months ago
Memory access scheduling
The bandwidth and latency of a memory system are strongly dependent on the manner in which accesses interact with the “3-D” structure of banks, rows, and columns characteristi...
Scott Rixner, William J. Dally, Ujval J. Kapasi, P...
MSE
2000
IEEE
174views Hardware» more  MSE 2000»
15 years 11 months ago
Integrating a Digital Camera in the Home Environment: Architecture and Prototype
Electronic photography is gaining parts of the photography market and tends to replace gradually all argentic photography. The combination of digital camera and computer technolog...
Nadia Bennani