Sciweavers

2620 search results - page 347 / 524
» Efficient Hardware Voxelization
Sort
View
FCCM
2005
IEEE
131views VLSI» more  FCCM 2005»
16 years 12 days ago
Automating the Layout of Reconfigurable Subsystems Using Circuit Generators
When designing systems-on-a-chip (SoCs), a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be ...
Shawn Phillips, Scott Hauck
IEEEICCI
2005
IEEE
16 years 11 days ago
A brain-like computer for cognitive software applications: the Ersatz Brain project
We want to design a suitable computer for the efficient execution of the software now being developed that will display human-like cognitive abilities. Examples of these potential...
J. A. Anderson
ISCA
2005
IEEE
121views Hardware» more  ISCA 2005»
16 years 11 days ago
Direct Cache Access for High Bandwidth Network I/O
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
170
Voted
ISCAS
2005
IEEE
126views Hardware» more  ISCAS 2005»
16 years 11 days ago
Scheduling algorithm for partially parallel architecture of LDPC decoder by matrix permutation
— The fully parallel LDPC decoding architecture can achieve high decoding throughput, but it suffers from large hardware complexity caused by a large set of processing units and ...
In-Cheol Park, Se-Hyeon Kang
ISCAS
2005
IEEE
166views Hardware» more  ISCAS 2005»
16 years 11 days ago
Extending SystemC to support mixed discrete-continuous system modeling and simulation
—Systems on chip are more and more heterogeneous and include software, analog/RF and digital hardware, and non-electronic components such as sensors or actuators. The design and ...
Alain Vachoux, Christoph Grimm, Karsten Einwich