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DATE
2005
IEEE
96views Hardware» more  DATE 2005»
16 years 12 days ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
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DATE
2005
IEEE
88views Hardware» more  DATE 2005»
16 years 12 days ago
System Synthesis for Networks of Programmable Blocks
The advent of sensor networks presents untapped opportunities for synthesis. We examine the problem of synthesis of behavioral specifications into networks of programmable sensor ...
Ryan Mannion, Harry Hsieh, Susan Cotterell, Frank ...
DATE
2005
IEEE
106views Hardware» more  DATE 2005»
16 years 12 days ago
SAT-Based Complete Don't-Care Computation for Network Optimization
This paper describes an improved approach to Boolean network optimization using internal don’t-cares. The improvements concern the type of don’t-cares computed, their scope, a...
Alan Mishchenko, Robert K. Brayton
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
16 years 12 days ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ECBS
2005
IEEE
160views Hardware» more  ECBS 2005»
16 years 12 days ago
Traceability-Driven Model Refinement for Test Case Generation
Testing complex Computer-Based Systems is not only a demanding but a very critical task. Therefore the use of models for generating test data is an important goal. Tool support du...
Matthias Riebisch, Michael Hübner