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TEI
2010
ACM
158views Hardware» more  TEI 2010»
16 years 1 months ago
ChainMail: a configurable multimodal lining to enable sensate surfaces and interactive objects
The ChainMail system is a scalable electronic sensate skin that is designed as a dense sensor network. ChainMail is built from small (1”x1”) rigid circuit boards attached to t...
Behram F. T. Mistree, Joseph A. Paradiso
ARITH
2009
IEEE
16 years 1 months ago
Fully Redundant Decimal Arithmetic
Hardware implementation of all the basic radix-10 arithmetic operations is evolving as a new trend in the design and implementation of general purpose digital processors. Redundan...
Saeid Gorgin, Ghassem Jaberipur
ISQED
2009
IEEE
94views Hardware» more  ISQED 2009»
16 years 1 months ago
Simultaneous buffer and interlayer via planning for 3D floorplanning
As technology advances, the interconnect delay among modules plays dominant role in chip performance. Buffer insertion, as a traditional approach to reduce wire delay in 2D ICs, i...
Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong
ISQED
2009
IEEE
86views Hardware» more  ISQED 2009»
16 years 1 months ago
Uncriticality-directed scheduling for tackling variation and power challenges
The advance in semiconductor technologies presents the serious problem of parameter variations. They affect threshold voltage of transistors and thus circuit delay has variability...
Toshinori Sato, Shingo Watanabe
ISPD
2009
ACM
79views Hardware» more  ISPD 2009»
16 years 1 months ago
A routing approach to reduce glitches in low power FPGAs
Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routi...
Quang Dinh, Deming Chen, Martin D. F. Wong