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ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 11 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
ICRA
1994
IEEE
127views Robotics» more  ICRA 1994»
15 years 11 months ago
"RISC" for Industrial Robotics: Recent Results and Open Problems
At the intersection of robotics, computational geometry, and manufacturingengineering, we have identifieda collection of research problems with near-term industrial applications. ...
John F. Canny, Kenneth Y. Goldberg
ITC
1993
IEEE
110views Hardware» more  ITC 1993»
15 years 11 months ago
Novel Test Pattern Generators for Pseudo-Exhaustive Testing
ÐPseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detecta...
Rajagopalan Srinivasan, Sandeep K. Gupta, Melvin A...
ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
15 years 10 months ago
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
Seongmoon Wang, Wenlong Wei
ASAP
2004
IEEE
127views Hardware» more  ASAP 2004»
15 years 10 months ago
A Public-Key Cryptographic Processor for RSA and ECC
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
Hans Eberle, Nils Gura, Sheueling Chang Shantz, Vi...