2620 search results - page 291 / 524 » Efficient Hardware Voxelization |
139
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
187
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
FPGA devices have witnessed popularity in their use for the rapid prototyping of biological Spiking Neural Network (SNNs) applications, as they offer the key requirement of reconf...
178
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FPL
2008
Springer
15 years 8 months ago
2008
Springer
This paper describes an analytical model, based principally on Rent's Rule, that relates logic architectural parameters to the area efficiency of an FPGA. In particular, the ...
182
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SBACPAD
2004
IEEE
15 years 8 months ago
2004
IEEE
Code compression has been used to minimize the memory area requirement of embedded systems. Recently, performance improvement and energy consumption reductionare observed as a by-...
164
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CDES
2009
15 years 7 months ago
2009
This paper develops a delay-insensitive (DI) digital design paradigm that utilizes ternary logic as an alternative to dual-rail logic for encoding the DATA and NULL states. This ne...