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CAV
2008
Springer
125views Hardware» more  CAV 2008»
15 years 8 months ago
Application of Formal Word-Level Analysis to Constrained Random Simulation
Abstract. Constrained random simulation is supported by constraint solvers integrated within simulators. These constraint solvers need to be fast and memory efficient to maintain s...
Hyondeuk Kim, HoonSang Jin, Kavita Ravi, Petr Spac...
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
15 years 8 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
DDECS
2008
IEEE
227views Hardware» more  DDECS 2008»
15 years 8 months ago
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator
The paper introduces a cryptographic System on a Chip (SoC) implementation based on recent Actel nonvolatile FPGA Fusion chip with embedded ARM7 soft-core processor. The SoC is bui...
Milos Drutarovsky, Michal Varchola
ECMDAFA
2008
Springer
97views Hardware» more  ECMDAFA 2008»
15 years 8 months ago
Textual Modelling Embedded into Graphical Modelling
Abstract. Today's graphical modelling languages, despite using symbols and connections, represent large model parts as structured text. We benefit from sophistic text editors,...
Markus Scheidgen
FPGA
2008
ACM
133views FPGA» more  FPGA 2008»
15 years 8 months ago
Vector processing as a soft-core CPU accelerator
The currently accepted method of accelerating applications in FPGA soft processor systems is to design a custom hardware accelerator. This paper suggests the alternative approach ...
Jason Yu, Guy Lemieux, Christopher Eagleston