2620 search results - page 284 / 524 » Efficient Hardware Voxelization |
149
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted t...
193
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ASPDAC
2007
ACM
15 years 10 months ago
2007
ACM
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
174
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CAV
2007
Springer
15 years 10 months ago
2007
Springer
In automatic software verification, we have observed a theoretical convergence of model checking and program analysis. In practice, however, model checkers are still mostly concern...
132
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
The process of sequential redundancy identification is the cornerstone of sequential synthesis and equivalence checking frameworks. The scalability of the proof obligations inhere...
199
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...