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ISLPED
1997
ACM
130views Hardware» more  ISLPED 1997»
15 years 11 months ago
Analytical energy dissipation models for low-power caches
We present detailed analytical models for estimating the energy dissipation in conventional caches as well as low energy cache architectures. The analytical models use the run tim...
Milind B. Kamble, Kanad Ghose
IPPS
1996
IEEE
15 years 10 months ago
A New Approach to Pipeline FFT Processor
A new VLSI architecture for real-time pipeline FFT processor is proposed. A hardware oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique ...
Shousheng He, Mats Torkelson
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
15 years 10 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
15 years 10 months ago
Algorithm selection: a quantitative computation-intensive optimization approach
Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalen...
Miodrag Potkonjak, Jan M. Rabaey
ICCAD
1994
IEEE
111views Hardware» more  ICCAD 1994»
15 years 10 months ago
On modeling top-down VLSI design
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
Bernd Schürmann, Joachim Altmeyer, Martin Sch...