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» Efficient Hardware Voxelization
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MSE
2000
IEEE
110views Hardware» more  MSE 2000»
15 years 11 months ago
Nobel Successive Elimination Algorithms for the Estimation of Motion Vectors
In this paper, we present fast algorithms to reduce the computations of block matching algorithms for motion estimation in video coding. Nobel Successive Elimination Algorithms fo...
Soo-Mok Jung, Sung-Chul Shin, Hyunki Baik, Myong-S...
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
15 years 11 months ago
Word Voter: A New Voter Design for Triple Modular Redundant Systems
Redundancy techniques are commonly used to design dependable systems to ensure high reliability, availability and data integrity. Triple Modular Redundancy (TMR) is a widely used ...
Subhasish Mitra, Edward J. McCluskey
ASPDAC
1999
ACM
116views Hardware» more  ASPDAC 1999»
15 years 11 months ago
An Automatic Router for the Pin Grid Array Package
A Pin-Grid-Array (PGA) package router is presented in this paper. Given a chip cavity with a number of I/O pads around its boundary and an equivalent number of pins distributed on...
Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chi...
ASPDAC
1999
ACM
149views Hardware» more  ASPDAC 1999»
15 years 11 months ago
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance
: In VLSI circuits with deep sub-micron, the parasitic capacitance from interconnect is a very important factor determining circuit performances such as power and time-delay. The B...
Jinsong Hou, Zeyi Wang, Xianlong Hong
ASPDAC
1999
ACM
144views Hardware» more  ASPDAC 1999»
15 years 11 months ago
Model Order Reduction of Large Circuits Using Balanced Truncation
A method is introduced for model order reduction of large circuits extracted from layout. The algorithm, which is based on balanced realization, can be used for reducing the order ...
Payam Rabiei, Massoud Pedram