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ITC
2003
IEEE
125views Hardware» more  ITC 2003»
15 years 12 months ago
Progressive Bridge Identification
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for...
Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Bla...
ITC
2003
IEEE
205views Hardware» more  ITC 2003»
15 years 12 months ago
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing
This paper describes a Hybrid DFT (H-DFT) architecture for low-cost, high quality structural testing in the high volume manufacturing (HVM) environment. This structure efficiently...
David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Ki...
ITC
2003
IEEE
146views Hardware» more  ITC 2003»
15 years 12 months ago
A New Approach for Low Power Scan Testing
As semiconductor manufacturing technology advances, power dissipation and noise in scan testing has become a critical problem. In our studies on practical LSI manufacturing, we ha...
Takaki Yoshida, Masafumi Watari
SBCCI
2003
ACM
135views VLSI» more  SBCCI 2003»
15 years 12 months ago
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic
The growing adoption of reconfigurable architectures opens new implementation alternatives and creates new design challenges. In the case of dynamically reconfigurable architectur...
Mauricio Ayala-Rincón, Rodrigo B. Nogueira,...
105
Voted
DATE
2010
IEEE
103views Hardware» more  DATE 2010»
15 years 11 months ago
A compact digital amplitude modulator in 90nm CMOS
—This paper presents a 90 nm CMOS digital amplitude modulator for polar transmitter. It reaches an output power of -2.5 dBmRMS using a WLAN OFDM 64QAM modulation at 2.45GHz achie...
V. Chironi, Björn Debaillie, Andrea Baschirot...