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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
16 years 8 days ago
UML 2 and SysML: An Approach to Deal with Complexity in SoC/NoC Design
UML is gaining increased attention as a system design language, as indicated by current standardization activities such as the SysML initiative and the UML for SoC Forum. Moreover...
Yves Vanderperren, Wim Dehaene
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
16 years 8 days ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
ISCA
2005
IEEE
115views Hardware» more  ISCA 2005»
16 years 7 days ago
The V-Way Cache: Demand Based Associativity via Global Replacement
As processor speeds increase and memory latency becomes more critical, intelligent design and management of secondary caches becomes increasingly important. The efficiency of curr...
Moinuddin K. Qureshi, David Thompson, Yale N. Patt
MICRO
2005
IEEE
139views Hardware» more  MICRO 2005»
16 years 7 days ago
Shader Performance Analysis on a Modern GPU Architecture
This paper presents an analysis of the performance of the shader processing units in a modern Graphics Processor Unit (GPU) architecture using real graphic applications. The archi...
Victor Moya Del Barrio, Carlos González, Jo...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
16 years 7 days ago
Implementing a Scheme for External Deterministic Self-Test
A new method for test resource partitioning is introduced which keeps the design-for-test logic independent of the test set and moves the test pattern dependent information to an ...
Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valent...