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ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
16 years 3 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
ICCAD
2001
IEEE
103views Hardware» more  ICCAD 2001»
16 years 3 months ago
Interconnect Resource-Aware Placement for Hierarchical FPGAs
In this paper, we utilize Rent’s rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design c...
Amit Singh, Ganapathy Parthasarathy, Malgorzata Ma...
3DIC
2009
IEEE
146views Hardware» more  3DIC 2009»
16 years 1 months ago
A routerless system level interconnection network for 3D integrated systems
- This paper describes a new architectural paradigm for fully connected, single-hop system level interconnection networks. The architecture is scalable enough to meet the needs of ...
Kelli Ireland, Donald M. Chiarulli, Steven P. Levi...
HICSS
2009
IEEE
104views Biometrics» more  HICSS 2009»
16 years 1 months ago
Celebrating Diversity in Volunteer Computing
The computing resources in a volunteer computing system are highly diverse in terms of software and hardware type, speed, availability, reliability, network connectivity, and othe...
David P. Anderson, Kevin Reed
DATE
2009
IEEE
101views Hardware» more  DATE 2009»
16 years 1 months ago
A monitor interconnect and support subsystem for multicore processors
Abstract— In many current SoCs, the architectural interface to onchip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a...
Sailaja Madduri, Ramakrishna Vadlamani, Wayne Burl...