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ISCA
1996
IEEE
102views Hardware» more  ISCA 1996»
15 years 10 months ago
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
Simultaneous multithreading is a technique that permits multiple independent threads to issue multiple instructions each cycle. In previous work we demonstrated the performance po...
Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, He...
ANSS
2004
IEEE
15 years 10 months ago
Cache Simulation Based on Runtime Instrumentation for OpenMP Applications
To enable optimizations in memory access behavior of high performance applications, cache monitoring is a crucial process. Simulation of cache hardware is needed in order to allow...
Jie Tao, Josef Weidendorfer
ARC
2006
Springer
124views Hardware» more  ARC 2006»
15 years 10 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
SACRYPT
2000
Springer
145views Cryptology» more  SACRYPT 2000»
15 years 10 months ago
Camellia: A 128-Bit Block Cipher Suitable for Multiple Platforms - Design and Analysis
We present a new 128-bit block cipher called Camellia. Camellia supports 128-bit block size and 128-, 192-, and 256-bit keys, i.e. the same interface specifications as the Advanced...
Kazumaro Aoki, Tetsuya Ichikawa, Masayuki Kanda, M...
VLSISP
2008
145views more  VLSISP 2008»
15 years 6 months ago
Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box
Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the ...
Stefan Tillich, Martin Feldhofer, Thomas Popp, Joh...