Sciweavers

2620 search results - page 251 / 524
» Efficient Hardware Voxelization
Sort
View
FPL
2007
Springer
100views Hardware» more  FPL 2007»
16 years 24 days ago
Clock-Aware Placement for FPGAs
The programmable clock networks in FPGAs have a significant impact on overall power, area, and delay. Not only does the clock network itself dissipate a significant amount of powe...
Julien Lamoureux, Steven J. E. Wilton
FCCM
2005
IEEE
115views VLSI» more  FCCM 2005»
16 years 7 days ago
FIFO Communication Models in Operating Systems for Reconfigurable Computing
Increasing demands upon embedded systems for higher level services like networking, user interfaces and file system management, are driving growth in fully-featured operating syst...
John A. Williams, Neil W. Bergmann, X. Xie
ISCAS
2005
IEEE
129views Hardware» more  ISCAS 2005»
16 years 6 days ago
A reconfigurable architecture for scanning biosequence databases
—Unknown protein sequences are often compared to a set of known sequences (a database scan) to detect functional similarities. Even though efficient dynamic programming algorithm...
Timothy F. Oliver, Bertil Schmidt, Douglas L. Mask...
IWMM
1998
Springer
153views Hardware» more  IWMM 1998»
15 years 11 months ago
Compiler Support to Customize the Mark and Sweep Algorithm
Mark and sweep garbage collectors (GC) are classical but still very efficient automatic memory management systems. Although challenged by other kinds of systems, such as copying c...
Dominique Colnet, Philippe Coucaud, Olivier Zendra
CGO
2004
IEEE
15 years 10 months ago
Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
Efficient inter-thread value communication is essential for improving performance in Thread-Level Speculation (TLS). Although several mechanisms for improving value communication ...
Antonia Zhai, Christopher B. Colohan, J. Gregory S...