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ISCAS
2006
IEEE
120views Hardware» more  ISCAS 2006»
16 years 19 days ago
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing
— This paper describes a new architecture for a cellular processor array integrated circuit, which operates in both discreteand continuous-time domains. Asynchronous propagation ...
Alexey Lopich, Piotr Dudek
VLSISP
2008
203views more  VLSISP 2008»
15 years 6 months ago
FPGA-based System for Real-Time Video Texture Analysis
This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract 2nd -order statistical features from video frames. These features ...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
ICIP
2004
IEEE
16 years 8 months ago
Scalable video coding based on motion-compensated temporal filtering: complexity and functionality analysis
Video coding techniques yielding state-of-the-art compression performance require large amount of computational resources, hence practical implementations, which target a broad ma...
Fabio Verdicchio, Yiannis Andreopoulos, Tom Clerck...
ETS
2007
IEEE
94views Hardware» more  ETS 2007»
16 years 29 days ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
16 years 7 days ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...