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ICCAD
2005
IEEE
106views Hardware» more  ICCAD 2005»
16 years 3 months ago
New decompilation techniques for binary-level co-processor generation
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...
Greg Stiff, Frank Vahid
ISCA
1998
IEEE
124views Hardware» more  ISCA 1998»
15 years 11 months ago
Threaded Multiple Path Execution
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...
Steven Wallace, Brad Calder, Dean M. Tullsen
167
Voted
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
15 years 10 months ago
Compiler-driven FPGA-area allocation for reconfigurable computing
In this paper, we propose two FPGA-area allocation algorithms based on profiling results for reducing the impact on performance of dynamic reconfiguration overheads. The problem o...
Elena Moscu Panainte, Koen Bertels, Stamatis Vassi...
ECMDAFA
2010
Springer
138views Hardware» more  ECMDAFA 2010»
15 years 4 months ago
A UML 2.0 Profile to Model Block Cipher Algorithms
Abstract. Current mobile digital communication systems must implement rigorous operations to guarantee high levels of confidentiality and integrity during transmission of critical ...
Tomás Balderas-Contreras, Gustavo Rodr&iacu...
FCCM
2011
IEEE
331views VLSI» more  FCCM 2011»
14 years 10 months ago
Synthesis of Platform Architectures from OpenCL Programs
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
Muhsen Owaida, Nikolaos Bellas, Konstantis Dalouka...