Sciweavers

2620 search results - page 240 / 524
» Efficient Hardware Voxelization
Sort
View
MICRO
1992
IEEE
133views Hardware» more  MICRO 1992»
15 years 10 months ago
Code generation schema for modulo scheduled loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
B. Ramakrishna Rau, Michael S. Schlansker, Parthas...
ASPDAC
2007
ACM
158views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Symbolic Model Checking of Analog/Mixed-Signal Circuits
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
David Walter, Scott Little, Nicholas Seegmiller, C...
ARCS
2006
Springer
15 years 10 months ago
An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks
Abstract. Dynamic hardware reconfiguration is becoming a key technology in embedded system design that offers among others new potentials in dependable computing. To make system de...
Dirk Koch, Thilo Streichert, Steffen Dittrich, Chr...
DATE
2004
IEEE
133views Hardware» more  DATE 2004»
15 years 10 months ago
Channel Decoder Architecture for 3G Mobile Wireless Terminals
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In thirdgeneration...
Friedbert Berens, Gerd Kreiselmaier, Norbert Wehn
FMCAD
2000
Springer
15 years 10 months ago
Model Checking Synchronous Timing Diagrams
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
Nina Amla, E. Allen Emerson, Robert P. Kurshan, Ke...