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DATE
2004
IEEE
110views Hardware» more  DATE 2004»
15 years 10 months ago
Interactive Cosimulation with Partial Evaluation
We present a technique to improve the efficiency of hardware-software cosimulation, using design information known at simulator compile-time. The generic term for such optimizatio...
Patrick Schaumont, Ingrid Verbauwhede
DSD
2004
IEEE
122views Hardware» more  DSD 2004»
15 years 10 months ago
On the Packet-Switched Implementation of a Discrete-Time CNN
Cellular Neural Networks are widely used with real-time image processing's applications. Such systems can be efficiently realized using macro enriched fieldprogrammable gate-...
Suleyman Malki, Lambert Spaanenburg
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 10 months ago
Battery-aware code partitioning for a text to speech system
The advent of multi-core embedded processors has brought along new challenges for embedded system design. This paper presents an efficient, battery aware, code partitioning techni...
Anirban Lahiri, Anupam Basu, Monojit Choudhury, Sr...
ISCA
2000
IEEE
118views Hardware» more  ISCA 2000»
15 years 10 months ago
Smart Memories: a modular reconfigurable architecture
Trends in VLSI technology scaling demand that future computing devices be narrowly focused to achieve high performance and high efficiency, yet also target the high volumes and lo...
Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, Willi...
ASPDAC
1995
ACM
99views Hardware» more  ASPDAC 1995»
15 years 10 months ago
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping
- In this paper, we present a hardware-software cosimulation environment for heterogeneoussystems. To be an efficient system verification environment for the rapid prototyping of h...
Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon ...