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ISLPED
2000
ACM
101views Hardware» more  ISLPED 2000»
15 years 11 months ago
Design issues for dynamic voltage scaling
Processors in portable electronic devices generally have a computational load which has time-varying performance requirements. Dynamic Voltage Scaling is a method to vary the proc...
Thomas D. Burd, Robert W. Brodersen
ASPDAC
1999
ACM
100views Hardware» more  ASPDAC 1999»
15 years 11 months ago
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Teru...
DATE
1999
IEEE
85views Hardware» more  DATE 1999»
15 years 11 months ago
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks
As an at-speed solution to board-level interconnect testing, an enhanced boundary-scan architecture utilizing a combination of slightly modified boundary-scan cells and a user-def...
Jongchul Shin, Hyunjin Kim, Sungho Kang
ICCAD
1999
IEEE
109views Hardware» more  ICCAD 1999»
15 years 11 months ago
Transient sensitivity computation for transistor level analysis and tuning
This paper presents a general method for computing transient sensitivities using both the direct and adjoint methods in event driven controlled explicit simulation algorithms that...
Tuyen V. Nguyen, Peter O'Brien, David W. Winston
ISCAS
1999
IEEE
99views Hardware» more  ISCAS 1999»
15 years 11 months ago
CMOS gate modeling based on equivalent inverter
A method for modeling complex CMOS gates by the reduction of each gate to an effective equivalent inverter is introduced. The conducting and parasitic behavior of parallel and ser...
Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioa...