Sciweavers

2620 search results - page 227 / 524
» Efficient Hardware Voxelization
Sort
View
ITC
2003
IEEE
147views Hardware» more  ITC 2003»
15 years 12 months ago
Data flow within an open architecture tester
An open architecture tester allows a third party to develop its own instrument. Such a tester must be open in the sense that it needs to be able to integrate this instrument with ...
Maurizio Gavardoni
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
15 years 12 months ago
Convolutional Compaction of Test Responses
This paper introduces a finite memory compactor called convolutional compactor that provides compaction ratios of test responses in excess of 100x even for a very small number of ...
Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M...
MSS
2003
IEEE
113views Hardware» more  MSS 2003»
15 years 12 months ago
Design and Implementation of Multiple Addresses Parallel Transmission Architecture for Storage Area Network
In this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows...
Bin Meng, Patrick B. T. Khoo, T. C. Chong
ITC
2002
IEEE
102views Hardware» more  ITC 2002»
15 years 11 months ago
Fault Grading FPGA Interconnect Test Configurations
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used o...
Mehdi Baradaran Tahoori, Subhasish Mitra, Shahin T...
ASAP
2000
IEEE
141views Hardware» more  ASAP 2000»
15 years 11 months ago
Bit Permutation Instructions for Accelerating Software Cryptography
Permutation is widely used in cryptographic algorithms. However, it is not well-supported in existing instruction sets. In this paper, two instructions, PPERM3R and GRP, are propo...
Zhijie Shi, Ruby B. Lee