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ERSA
2009
107views Hardware» more  ERSA 2009»
15 years 4 months ago
Towards Effective Modeling and Programming Multi-core Tiled Reconfigurable Architectures
For a generic flexible efficient array antenna receiver platform a hierarchical reconfigurable tiled architecture has been proposed. The architecture provides a flexible reconfigur...
Kenneth C. Rovers, Marcel D. van de Burgwal, Jan K...
CVPR
2008
IEEE
16 years 8 months ago
High quality mesostructure acquisition using specularities
We propose a technique for cheap and efficient acquisition of mesostructure normal maps from specularities, which only requires a simple LCD monitor and a digital camera. Coded il...
Yannick Francken, Tom Cuypers, Tom Mertens, Jo Gie...
ICCD
2002
IEEE
127views Hardware» more  ICCD 2002»
16 years 3 months ago
GPE: A New Representation for VLSI Floorplan Problem
In this paper, we propose a new representation of VLSI floorplan and building block problem. The representation is the generalization of Polish expression [1]. By proposing a new ...
Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang
ICCD
2001
IEEE
90views Hardware» more  ICCD 2001»
16 years 3 months ago
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs
Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked...
Martin Saint-Laurent, Madhavan Swaminathan, James ...
DATE
2009
IEEE
133views Hardware» more  DATE 2009»
16 years 1 months ago
Pipelined data parallel task mapping/scheduling technique for MPSoC
—In this paper, we propose a multi-task mapping/scheduling technique for heterogeneous and scalable MPSoC. To utilize the large number of cores embedded in MPSoC, the proposed te...
Hoeseok Yang, Soonhoi Ha