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DATE
2006
IEEE
119views Hardware» more  DATE 2006»
16 years 19 days ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
DSD
2006
IEEE
73views Hardware» more  DSD 2006»
16 years 19 days ago
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications
We propose a novel two-level Boolean minimizer coming in succession to our previously developed minimizer BOOM, so we have named it BOOM-II. It is a combination of two minimizers,...
Petr Fiser, Hana Kubatova
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
16 years 18 days ago
FPGA-based architecture for real-time IP video and image compression
–Three-dimensional imaging applications require high resolution images that finally result in high data volumes. Due to bandwidth and storage restrictions, an efficient and robus...
Dimitris Maroulis, Nikos Sgouros, Dionisis Chaikal...
IPPS
2005
IEEE
16 years 5 days ago
Embedded MPLS Architecture
This paper presents a hardware architecture for Multi Protocol Label Switching (MPLS). MPLS is a protocol used primarily to prioritize internet traffic and improve bandwidth utili...
Raymond Peterkin, Dan Ionescu
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 12 months ago
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification
This paper presents a new and low-cost approach for identifying sequentially untestable faults. Unlike the single fault theorem, where the stuck-at fault is injected only in the r...
Manan Syal, Michael S. Hsiao