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JPDC
2006
95views more  JPDC 2006»
15 years 6 months ago
Speculative pre-execution assisted by compiler (SPEAR)
Speculative pre-execution achieves efficient data prefetching by running additional prefetching threads on spare hardware contexts. Various implementations for speculative pre-exe...
Won Woo Ro, Jean-Luc Gaudiot
PROCEDIA
2010
138views more  PROCEDIA 2010»
15 years 1 months ago
Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics
Currently several computational problems require high processing power to handle huge amounts of data, although underlying core algorithms appear to be rather simple. Especially i...
Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Car...
ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
16 years 3 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
16 years 1 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
DATE
2010
IEEE
181views Hardware» more  DATE 2010»
15 years 11 months ago
Temperature-aware dynamic resource provisioning in a power-optimized datacenter
- The current energy and environmental cost trends of datacenters are unsustainable. It is critically important to develop datacenter-wide power and thermal management (PTM) soluti...
Ehsan Pakbaznia, Mohammad Ghasemazar, Massoud Pedr...