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DATE
2006
IEEE
134views Hardware» more  DATE 2006»
16 years 18 days ago
ASIP-based multiprocessor SoC design for simple and double binary turbo decoding
This paper presents a new multiprocessor platform for high throughput turbo decoding. The proposed platform is based on a new configurable ASIP combined with an efficient memory a...
Olivier Muller, Amer Baghdadi, Michel Jéz&e...
IOLTS
2000
IEEE
115views Hardware» more  IOLTS 2000»
15 years 11 months ago
Micro-Checkpointing: Checkpointing for Multithreaded Applications
In this paper, we introduce an efficient technique for checkpointing multithreaded applications. Our approach makes use of processes constructed around the ARMOR (Adaptive Reconfi...
Keith Whisnant, Zbigniew Kalbarczyk, Ravishankar K...
ISLPED
2000
ACM
99views Hardware» more  ISLPED 2000»
15 years 11 months ago
Practical considerations of clock-powered logic
Recovering and reusing circuit energies that would otherwise be dissipated as heat can reduce the power dissipated by a VLSI chip. To accomplish this requires a power source that ...
William C. Athas
MICRO
1990
IEEE
147views Hardware» more  MICRO 1990»
15 years 10 months ago
Motivation and framework for using genetic algorithms for microcode compaction
Genetic algorithms are a robust adaptive optimization technique based on a biological paradigm. They perform efficient search on poorly-defined spaces by maintaining an ordered po...
Steven J. Beaty, Darrell Whitley, Gearold Johnson
AISS
2010
155views more  AISS 2010»
15 years 4 months ago
An Adaptive HW/SW Dual Communication Mode
HW/SW communication mode makes significant impact on HW/SW communication efficiency. Based on the characteristics of the hardware functions, this paper presents an adaptive HW/SW ...
Wang-xian Yang, Dong-hua Liu, Ding-ju Zhu