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ICCAD
2009
IEEE
126views Hardware» more  ICCAD 2009»
15 years 4 months ago
Timing Arc based logic analysis for false noise reduction
The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it ...
Murthy Palla, Jens Bargfrede, Stephan Eggersgl&uum...
ISCAS
2002
IEEE
107views Hardware» more  ISCAS 2002»
15 years 11 months ago
H.26L-based fine granularity scalable video coding
This paper proposes an efficient scalable coding scheme with fine-grain scalability, where the base layer is encoded with H.26L, and the enhancement layer is encoded with PFGS cod...
Yuwen He, Feng Wu, Shipeng Li, Yuzhuo Zhong, Shiqi...
MTV
2005
IEEE
101views Hardware» more  MTV 2005»
16 years 3 days ago
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores
Semiconductor manufacturers aim at deliver new devices within shorter times in order to gain market shares. First silicon debug is an important issue in order to minimize the time...
Paolo Bernardi, Michelangelo Grosso, Maurizio Reba...
EH
2000
IEEE
123views Hardware» more  EH 2000»
15 years 11 months ago
The Test Vector Problem and Limitations to Evolving Digital Circuits
How do we know the correctness of an evolved circuit? While Evolutionary Hardware is exhibiting its effectiveness, we argue that it is very difficult to design a large-scale digit...
Kosuke Imamura, James A. Foster, Axel W. Krings
OSDI
1994
ACM
15 years 7 months ago
PathFinder: A Pattern-Based Packet Classifier
This paper describes a pattern-based approach to building packet classifiers. One novelty of the approach is that it can be implemented efficiently in both software and hardware. ...
Mary L. Bailey, Burra Gopal, Michael A. Pagels, La...