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HPCA
2006
IEEE
16 years 6 months ago
An approach for implementing efficient superscalar CISC processors
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E...
ICC
2007
IEEE
128views Communications» more  ICC 2007»
16 years 26 days ago
Delay and Power Efficient Voice Transmission over MANET
: Increasing speed of hardware device and versatile functionalities of small equipments e.g. laptop, PDA etc. are introducing various voice oriented applications with mobility. Lik...
Md. Golam Kaosar, Tarek R. Sheltami, Ashraf S. Has...
CHES
2007
Springer
111views Cryptology» more  CHES 2007»
16 years 21 days ago
TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks
Replay attacks are often the most costly attacks to thwart when dealing with off-chip memory integrity. With a trusted System-on-Chip, the existing countermeasures against replay r...
Reouven Elbaz, David Champagne, Ruby B. Lee, Lione...
IESS
2007
Springer
92views Hardware» more  IESS 2007»
16 years 20 days ago
An Interactive Model Re-Coder for Efficient SoC Specification
To overcome the complexity in System-on-Chip (SoC) design, researchers have developed sophisticated design flows that significantly reduce the development time through automation...
Pramod Chandraiah, Rainer Dömer
LCN
2006
IEEE
16 years 16 days ago
Efficient Packet Processing in User-Level OSes: A Study of UML
Network server consolidation has become popular through recent virtualization technology that builds secure, isolated network systems on shared hardware. One of the virtualization...
Younggyun Koh, Calton Pu, Sapan Bhatia, Charles Co...