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DATE
2006
IEEE
91views Hardware» more  DATE 2006»
15 years 10 months ago
Efficient incremental clock latency scheduling for large circuits
The clock latency scheduling problem is usually solved on the sequential graph, also called register-to-register graph. In practice, the the extraction of the sequential graph for...
Christoph Albrecht
ASPDAC
2001
ACM
103views Hardware» more  ASPDAC 2001»
15 years 10 months ago
Efficient minimum spanning tree construction without Delaunay triangulation
Given n points in a plane, a minimum spanning tree is a set of edges which connects all the points and has a minimum total length. A naive approach enumerates edges on all pairs o...
Hai Zhou, Narendra V. Shenoy, William Nicholls
ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
15 years 10 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson
HOTDEP
2008
168views Hardware» more  HOTDEP 2008»
15 years 8 months ago
A Spin-Up Saved Is Energy Earned: Achieving Power-Efficient, Erasure-Coded Storage
Storage accounts for a significant amount of a data center's ever increasing power budget. As a consequence, energy consumption has joined performance and reliability as a do...
Kevin M. Greenan, Darrell D. E. Long, Ethan L. Mil...
ASAP
2007
IEEE
97views Hardware» more  ASAP 2007»
15 years 8 months ago
FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers
This paper presents an optimized design approach of two’s complement large-size squarers using embedded multipliers in FPGAs. The realization is based on BaughWooley’s algorit...
Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, ...